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<title>BNDMOV—Move Bounds </title></head>
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<h1>BNDMOV—Move Bounds</h1>
<table>
<tr>
<th>Opcode/Instruction</th>
<th>Op/En</th>
<th>64/32 bit Mode Support</th>
<th>CPUID Feature Flag</th>
<th>Description</th></tr>
<tr>
<td>66 0F 1A /r BNDMOV bnd1, bnd2/m64</td>
<td>RM</td>
<td>NE/V</td>
<td>MPX</td>
<td>Move lower and upper bound from bnd2/m64 to bound register bnd1.</td></tr>
<tr>
<td>66 0F 1A /r BNDMOV bnd1, bnd2/m128</td>
<td>RM</td>
<td>V/NE</td>
<td>MPX</td>
<td>Move lower and upper bound from bnd2/m128 to bound register bnd1.</td></tr>
<tr>
<td>66 0F 1B /r BNDMOV bnd1/m64, bnd2</td>
<td>MR</td>
<td>NE/V</td>
<td>MPX</td>
<td>Move lower and upper bound from bnd2 to bnd1/m64.</td></tr>
<tr>
<td>66 0F 1B /r BNDMOV bnd1/m128, bnd2</td>
<td>MR</td>
<td>V/NE</td>
<td>MPX</td>
<td>Move lower and upper bound from bnd2 to bound register bnd1/m128.</td></tr></table>
<h3>Instruction Operand Encoding</h3>
<table>
<tr>
<td>Op/En</td>
<td>Operand 1</td>
<td>Operand 2</td>
<td>Operand 3</td></tr>
<tr>
<td>RM</td>
<td>ModRM:reg (w)</td>
<td>ModRM:r/m (r)</td>
<td>NA</td></tr>
<tr>
<td>MR</td>
<td>ModRM:r/m (w)</td>
<td>ModRM:reg (r)</td>
<td>NA</td></tr></table>
<h2>Description</h2>
<p>BNDMOV moves a pair of lower and upper bound values from the source operand (the second operand) to the destination (the first operand). Each operation is 128-bit move. The exceptions are same as the MOV instruction. The memory format for loading/store bounds in 64-bit mode is shown in Figure 3-5.</p>
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<text y="65346.6135" x="395.3984" style="font-size:6.932300pt" lengthAdjust="spacingAndGlyphs" textLength="110.22357">BNDMOV to memory in 64-bit mode</text>
<text y="65379.6735" x="458.459" style="font-size:6.932300pt" lengthAdjust="spacingAndGlyphs" textLength="3.8543588">0</text>
<text y="65380.1535" x="131.58" style="font-size:6.932300pt" lengthAdjust="spacingAndGlyphs" textLength="7.69346654">16</text>
<text y="65380.2135" x="305.52" style="font-size:6.932300pt" lengthAdjust="spacingAndGlyphs" textLength="3.8543588">8</text>
<text y="65380.5135" x="470.0378" style="font-size:6.932300pt" lengthAdjust="spacingAndGlyphs" textLength="32.4015702">Byte offset</text>
<text y="65430.7934" x="387.7784" style="font-size:6.932300pt" lengthAdjust="spacingAndGlyphs" textLength="110.1473147">BNDMOV to memory in 32-bit mode</text>
<text y="65463.9135" x="450.839" style="font-size:6.932300pt" lengthAdjust="spacingAndGlyphs" textLength="3.8543588">0</text>
<text y="65464.3334" x="123.96" style="font-size:6.932300pt" lengthAdjust="spacingAndGlyphs" textLength="7.69346654">16</text>
<text y="65464.3935" x="297.9" style="font-size:6.932300pt" lengthAdjust="spacingAndGlyphs" textLength="3.8543588">8</text>
<text y="65464.3935" x="378.9" style="font-size:6.932300pt" lengthAdjust="spacingAndGlyphs" textLength="3.8543588">4</text>
<text y="65464.6934" x="462.4781" style="font-size:6.932300pt" lengthAdjust="spacingAndGlyphs" textLength="32.4085025">Byte offset</text>
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<text y="65350.4535" x="132.9" style="font-size:6.932300pt" lengthAdjust="spacingAndGlyphs" textLength="56.66808635">Upper Bound (UB)</text>
<text y="65350.5135" x="258.5992" style="font-size:6.932300pt" lengthAdjust="spacingAndGlyphs" textLength="55.4584">Lower Bound (LB)</text>
<text y="65434.6935" x="125.28" style="font-size:6.932300pt" lengthAdjust="spacingAndGlyphs" textLength="56.59183105">Upper Bound (UB)</text>
<text y="65434.6935" x="250.962599" style="font-size:6.932300pt" lengthAdjust="spacingAndGlyphs" textLength="55.47573075">Lower Bound (LB)</text></svg>
<h3>Figure 3-5.  Memory Layout of BNDMOV to/from Memory</h3>
<p>This instruction does not change flags.</p>
<h2>Operation</h2>
<p><strong>BNDMOV register to register</strong></p>
<pre>DEST.LB (cid:197) SRC.LB;
DEST.UB (cid:197) SRC.UB;</pre>
<p><strong>BNDMOV from memory</strong></p>
<pre>IF 64-bit mode THEN
         DEST.LB (cid:197) LOAD_QWORD(SRC);
         DEST.UB (cid:197) LOAD_QWORD(SRC+8);
    ELSE
         DEST.LB (cid:197) LOAD_DWORD_ZERO_EXT(SRC);
         DEST.UB (cid:197) LOAD_DWORD_ZERO_EXT(SRC+4);
FI;</pre>
<p><strong>BNDMOV to memory</strong></p>
<pre>IF 64-bit mode THEN
         DEST[63:0] (cid:197) SRC.LB;
         DEST[127:64] (cid:197) SRC.UB;
    ELSE
         DEST[31:0] (cid:197) SRC.LB;
         DEST[63:32] (cid:197) SRC.UB;
FI;</pre>
<h2>Intel C/C++ Compiler Intrinsic Equivalent</h2>
<p>BNDMOV</p>
<p>void * _bnd_copy_ptr_bounds(const void *q, const void *r)</p>
<h2>Flags Affected</h2>
<p>None</p>
<h2>Protected Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#UD</td>
<td>
<p>If the LOCK prefix is used but the destination is not a memory operand.</p>
<p>If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.</p>
<p>If 67H prefix is not used and CS.D=0.</p>
<p>If 67H prefix is used and CS.D=1.</p></td></tr>
<tr>
<td>#SS(0)</td>
<td>If the memory operand effective address is outside the SS segment limit.</td></tr>
<tr>
<td>#GP(0)</td>
<td>
<p>If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</p>
<p>If the destination operand points to a non-writable segment</p>
<p>If the DS, ES, FS, or GS segment register contains a NULL segment selector.</p></td></tr>
<tr>
<td>#AC(0)</td>
<td>If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.</td></tr>
<tr>
<td>#PF(fault code)</td>
<td>If a page fault occurs.</td></tr></table>
<h2>Real-Address Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#UD</td>
<td>
<p>If the LOCK prefix is used but the destination is not a memory operand.</p>
<p>If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.</p>
<p>If 16-bit addressing is used.</p></td></tr>
<tr>
<td>#GP(0)</td>
<td>If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr>
<td>#SS</td>
<td>If the memory operand effective address is outside the SS segment limit.</td></tr></table>
<h2>Virtual-8086 Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#UD</td>
<td>
<p>If the LOCK prefix is used but the destination is not a memory operand.</p>
<p>If ModRM.r/m encodes BND4-BND7 when Intel MPX is enabled.</p>
<p>If 16-bit addressing is used.</p></td></tr>
<tr>
<td>#GP(0)</td>
<td>If the memory operand effective address is outside the CS, DS, ES, FS, or GS segment limit.</td></tr>
<tr>
<td>#SS(0)</td>
<td>If the memory operand effective address is outside the SS segment limit.</td></tr>
<tr>
<td>#AC(0)</td>
<td>If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.</td></tr>
<tr>
<td>#PF(fault code)</td>
<td>If a page fault occurs.</td></tr></table>
<h2>Compatibility Mode Exceptions</h2>
<p>Same exceptions as in protected mode.</p>
<h2>64-Bit Mode Exceptions</h2>
<table class="exception-table">
<tr>
<td>#UD</td>
<td>
<p>If the LOCK prefix is used but the destination is not a memory operand.</p>
<p>If ModRM.r/m and REX encodes BND4-BND15 when Intel MPX is enabled.</p></td></tr>
<tr>
<td>#SS(0)</td>
<td>If the memory address referencing the SS segment is in a non-canonical form.</td></tr>
<tr>
<td>#GP(0)</td>
<td>If the memory address is in a non-canonical form.</td></tr>
<tr>
<td>#AC(0)</td>
<td>If alignment checking is enabled and an unaligned memory reference is made while CPL is 3.</td></tr>
<tr>
<td>#PF(fault code)</td>
<td>If a page fault occurs.</td></tr></table></body></html>